Immediate job Opportunity for Physical Design engineer / Managers. Kindly send in your updated Profiles to the email address below or call me.
Lead Level Professionals in Physical Design
Experience : More than 5-10 years education: Bachelors or Masters Degree in engineering
Experienced Senior level physical design engineers with 5-10 years of hands on design experience and having participated in at least 3-4 full chip tapeouts.
- Work experience covering multimillion gate SOC physical implementations from netlist to GDSII on 65nm and below technologies. 45nm/32nm/28nm technology experience preferred.
- Complete Block level physical implementation from netlist to sign-off quality GDSII using Cadence Encounter/Synopsys Icc/Magma Talus Place&Route platforms
- Experience leading small teams of engineers would be helpful
- Good exposure to the following areas and expert level proficiency in 1-2 sub-domains covering:
--Power delivery and IR analysis
--Clock tree synthesis
--Budgeting, Static Timing Analysis and closure activities(including SI & MMMC)
--Deep-sub micron effects 65nm and below including OCV, DFM, DFY etc.
--Experience with low power implementation methods and techniques
--Expert level user in at least one of: Cadence, Synopsys, Magma Physical Implementation Tools.
--Moderate to high levels of PERL, TCL, AWK scripting skills.