Candidate should have 3-8 years of experience in Verification.
Should have expertise in System Verilog .Experience with UVM/OVM/VMM will be added advantage.
Should have worked on interfaces like PCIe,HDMI,XAUI,SPI.2 etc.
Job Requirement :
Individual contributor, should be able to code/write test cases, good spec understanding, good debugging skills.
Interested candidates can send the CV's to firstname.lastname@example.org